The reception of digital signals requires that the receiver correctly samples each of the bits or pulses in the incoming pulse train. Bit sampling is conventionally accomplished by a locally generated timing wave signal which is maintained in phase with the incoming signals. A known implementation for maintaining a generated timing wave signal in phase with a pulse train comprises a phase locked loop. The principal components of the phase locked loop consist of a phase controllable wave generator and a phase comparator for comparing the phase of transitions of the generated wave with the phase of transitions of the incoming signals. Each comparison results in a phase error output signal whose magnitude defines the magnitude of the difference in phase between the timing wave and the input signals and whose polarity defines whether the timing wave signals lead or lag the phase of the input signals. Phase error outputs of the comparator are then used to modify the relative phase of the generated output wave with respect to the phase of the input signals in a direction that will achieve bit synchronization.
The incoming signals are, of course, subject to interferences such as noise. Noise signals can generally be filtered or blocked out before they reach the phase locked loop but it is inevitable that some of the noise will occasionally get through. Noise signals may therefore be applied to the comparator and the occasional noise signal transition may be interpreted by the phase comparator as being derived from the incoming signals. The consequent phase comparison of noise and the timing wave by the comparator improperly modifies the wave generator phase. It is a broad object of the invention to maintain a locally generated timing wave in phase with incoming signals which are subject to interferences. It is a more specific object to distinguish between digital signal transitions and occasional interference signal transitions.
In U.S. Pat. No. 3,488,440, which issued to M. A. Logan and H. C. Schroeder on Jan. 6, 1970, there is disclosed a timing wave recovery circuit that provides a solution to the incoming signal interference problem. In accordance therewith, a plurality of phase comparisons are analyzed over a time interval. A phase modification of the timing wave signal is made at the termination of the interval in accordance with the analysis. In the analysis, any occasional phase comparison inconsistent with other comparisons is ignored, since the occasional inconsistent comparison is likely due to an incoming noise transition. This type of phase correction, however, results in substantial intervals between corrections.
It may be desirable to rapidly correct the timing wave phase, such as when a large phase angle error exists. The H. A. Logan et al patent disclosed an arrangement whereby the analysis interval may be substantially reduced or phase corrections may be made for each phase comparison. This arrangement, as disclosed in the M. A. Logan et al patent, is relatively complex and complicated. Moreover, the arrangement becomes more vulnerable to noise when the analysis period is reduced and further vulnerable to noise when corrections are made for each comparison.
Accordingly, it is a further object of this invention to provide a simple and uncomplicated arrangement which rapidly phase synchronizes a timing wave signal with an incoming signal subject to noise.